The present invention relates to a thermal processing furnace for processing semiconductor wafers, and particularly to a vertical-type heat processing furnace.
Thermal processing furnaces, also known as diffusion furnaces, have been widely known and used for many years to perform a variety of semiconductor fabrication processes, including annealing, diffusion, oxidation, and chemical vapor deposition. As a result, these processes are well understood, especially with regard to the impact of process variables on the quality and uniformity of resulting products. Thermal processing furnaces typically employ either a horizontal-type furnace or a vertical-type furnace. For some applications, vertical-type furnaces are preferred because they create less particles during use, thus decreasing the incidence of contamination and wafer waste, they can be easily automated, and they require less floor space because of their relatively small footprint.
Both conventional types of diffusion furnaces are designed to heat semiconductor wafers to desired temperatures to promote either diffusion of the dopants to a desired depth while maintaining line width smaller than 1 micron, as known, or to perform other conventional processing techniques such as the application of an oxide layer to the wafer or deposition of a chemical vapor layer to the wafer. The heating requirements of the wafer during processing are known and well understood, and thus are closely monitored.
Conventional vertical-type thermal processing furnaces are designed to support the processing tube within the furnace in the vertical position. The thermal furnace also typically employs a wafer boat assembly which is mounted to appropriate translation mechanisms for moving the wafer boat into and out of the processing tube. A wafer-handling assembly is deployed adjacent and parallel to the wafer-boat assembly to transfer the semiconductor wafers from wafer cassettes, which typically hold up to 100 wafers, to the wafer-boat assembly. The wafer-handling assembly is typically located in a loadlock chamber separate from the chamber housing the process tube, and whose environment is closely controlled by appropriate monitoring structure. The loadlock mounting the wafer-handling assembly can also be isolated from the wafer cassettes, such as by mounting the wafer cassettes in one or more loadlocks that are in selected fluid communication with the wafer-handling assembly loadlock. The serial chain of loadlocks thus allows the precise environmental control necessary during processing to decrease or eliminate the chance of contaminants being formed in the wafer during heating. The loadlocks are typically separated from each other by gate valves that are selectively opened and closed to allow the transfer of a wafer from the wafer cassette to the wafer boat and vice versa.
In practice, after a vacuum is established in the loadlock chamber mounting the wafer boat, an inert gas such as nitrogen can be introduced to fill the loadlock chamber and to remove air therefrom. This purging of air from the loadlock chamber prevents the formation of natural oxide films on the semiconductor wafer surface. As noted above, the loadlock chamber is connected to other serial loadlocks which house the semiconductor wafers cassettes and the wafer handling assembly, to thus effectuate loading and unloading of the wafer boat in a nitrogen atmosphere. The wafer boat is then loaded with wafers from the wafer cassette via the wafer-handling assembly to form a wafer batch. The batch is then disposed within the furnace, where it undergoes a user-selected process under elevated temperatures. Conventional vertical furnaces of these types are shown and described in U.S. Pat. No. 5,217,501 of Fuse et al. and in U.S. Pat. No. 5,387,265 of Kakizaki et al.
Prior furnaces establish an isothermal zone within the process tube that extends between about 20 inches and about 30 inches, where a wafer batch having between about 150 to 200 wafers is disposed. Due to the relatively large thermal mass associated with this wafer batch, the temperature ramp-up rates are relatively small, for example, between about 5.degree. C./min. and about 10.degree. C./min, and the temperature ramp-down rates are relatively small, for example, between about 2.5.degree. C./min. and about 5.degree. C./min. This results in a relatively long thermal cycle per batch, and thus a relatively large thermal budget per wafer.
Another drawback of these and other conventional vertical-type thermal processing furnaces is that they achieve relatively low throughput because of the increased cycle time per batch. These conventional systems are thus not uniquely situated to accommodate today's ever increasing demands for semiconductor wafers.
Another drawback of these furnaces is that they incorporate pre-staging loadlock assemblies which form air-free environments for the transfer of wafers to and from the wafer boat. The time involved in venting and purging the loadlocks to achieve these states increases the overall processing time per batch and thus serves to further decrease the throughput of the furnace system.
Still another drawback is that these furnaces have a relatively large footprint and occupy relatively large amounts of floor space in clean rooms, thus providing for inefficient use of expensive clean room space.
Due to the foregoing and other shortcomings of prior art vertical-type thermal processing furnaces, an object of the present invention is to provide a vertical-type furnace that provides for relatively high throughput.
Another object of the invention is to provide a furnace that achieves improved temperature ramp-up and ramp-down rates.
Still another object of the invention is to provide a thermal processing furnace that can be easily automated and occupies relatively small floor space.
Other general and more specific objects of the invention will in part be obvious and will in part appear from the drawings and description which follow.